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CS5460 Single Phase Bi-Directional Power/Energy IC
Features
l Energy
Description
The CS5460 is a highly integrated Analog-to-Digital Converter (ADC) which combines two ADCs, high speed power calculation functions, and a serial interface on a single chip. It is designed to accurately measure and calculate: Energy, Instantaneous Power, IRMS, and VRMS for single phase 2 or 3-wire power meter applications. The CS5460 interfaces to a low cost shunt or transformer to measure current, and resistive divider or transformer to measure voltage. The CS5460 features a bi-directional serial interface for communication with a micro-controller and a fixed-width programmable frequency output that is proportional to energy. The product is initialized and fully functional upon power-up, and includes facilities for system-level calibration under control of the user program.
Data Linearity: 0.1% of Reading over 1000:1 Dynamic Range l On-Chip Functions: Energy, I V, IRMS and VRMS, Energy to Pulse-Rate Conversion l Complies with IEC 687/1036, JIS l Power Consumption <12 mW l Interface Optimized for Shunt Sensor l Phase Compensation l Ground-Referenced Signals with Single Supply l System Calibration l On-chip 2.5 V Reference (60 ppm/C drift) l Simple Three-wire Serial Interface l Watch Dog Timer l Power Supply Monitor l Power Supply Configurations
- VA+ = +5 V; VA- = 0V; VD+ = +3 V to +5 V - VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V
VA+
ORDERING INFORMATION: CS5460-BS
RESET High Pass Filter
-40C to +85C
VD+ Watch Dog Timer
24-pin SSOP
IIN+ IIN-
PGA x10,x50 4th Order Modulator Digital Filter
CS Power Calculation Engine (Energy I*V I RMS ,V RMS ) SDI Serial Interface SDO SCLK INT EDIR High Pass Filter E-to-F EOUT
VIN+ VIN-
x10
2nd Order Modulator
Digital Filter
VREFIN
x1
VREFOUT
Voltage Reference
Power Monitor
System Clock
/K
Clock Generator
Calibration SRAM
VA-
PFMON
XIN
XOUT CPUCLK
DGND
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2000 (All Rights Reserved)
JAN `00 DS279PP5 1
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TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ............................................................ 4 ANALOG CHARACTERISTICS ............................................................................... 4 5 V DIGITAL CHARACTERISTICS ......................................................................... 5 3 V DIGITAL CHARACTERISTICS ......................................................................... 6 ABSOLUTE MAXIMUM RATINGS .......................................................................... 6 SWITCHING CHARACTERISTICS ......................................................................... 7 2. GENERAL DESCRIPTION ........................................................................................... 9 2.1 Theory of Operation........................................................................................... 9 2.2 Performing Measurements .............................................................................. 10 2.2.1 Single Computation Cycle (C = 0).......................................................... 11 2.2.2 Multiple Computation Cycles (C = 1)...................................................... 11 2.3 High Rate Digital Filters ................................................................................... 11 2.4 Pulse-Rate Output ........................................................................................... 12 3. SERIAL PORT OVERVIEW ........................................................................................ 14 3.1 Command Word (Write Only) .......................................................................... 15 3.1.1 Start Conversions ............................................................................... 15 3.1.2 SYNC0 Command .............................................................................. 15 3.1.3 SYNC1 Command ............................................................................. 15 3.1.4 Power-up/Halt Control ........................................................................ 15 3.1.5 Power-down Control ............................................................................. 16 3.1.6 Calibration Control ............................................................................ 16 3.1.7 Register Read/Write Command ......................................................... 17 3.2 Serial Port Interface ......................................................................................... 18 3.3 Serial Port Initialization .................................................................................... 18 3.4 System Initialization ......................................................................................... 20 4. REGISTER DESCRIPTION ........................................................................................ 21 4.1 Configuration Register .................................................................................... 21 4.2 Current Offset Register and Voltage Offset Register ...................................... 22 4.3 Current Gain Register and Voltage Gain Register .......................................... 22 4.4 Cycle Count Register ...................................................................................... 23 4.5 Pulse-Rate Register ........................................................................................ 23 4.6 I,V,P,E Signed Output Register Results ......................................................... 23 4.7 IRMS, VRMS Unsigned Output Register Results ........................................... 23 4.8 Timebase Calibration ...................................................................................... 24 4.9 Status Register and Mask Register ................................................................ 24
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Microwire is a trademark of National Semiconductor Corporation. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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5. FUNCTIONAL DESCRIPTION ................................................................................... 26 5.1 Interrupt and Watchdog Timer......................................................................... 26 5.1.1 Interrupt.................................................................................................. 26 5.1.1.1 Clearing the Status Register ........................................................ 26 5.1.1.2 Typical use of the INT pin............................................................. 26 5.1.1.3 INT Active State ........................................................................... 26 5.1.1.4 Exceptions .................................................................................... 26 5.1.2 Watch Dog Timer ................................................................................... 26 5.2 Oscillator Characteristics................................................................................. 27 5.3 Analog Inputs .................................................................................................. 27 5.4 Voltage Reference........................................................................................... 28 5.5 Performing Calibrations ................................................................................... 28 5.5.1 System Calibration................................................................................. 28 5.5.2 Calibration Tips ...................................................................................... 29 5.6 Input Current Protection .................................................................................. 29 5.7 PCB Layout ..................................................................................................... 30 6. PIN DESCRIPTION..................................................................................................... 31 7. SPECIFICATION DEFINITIONS................................................................................. 32 8. PACKAGE DIMENSIONS .......................................................................................... 33
LIST OF FIGURES
Figure 1. SDI Write Timing (Not to Scale)....................................................................................... 8 Figure 2. SDO Read Timing (Not to Scale)..................................................................................... 8 Figure 3. Typical Connection Diagram (One-Phase 2-Wire)........................................................... 9 Figure 4. Typical Connection Diagram (One-Phase 3-Wire)......................................................... 10 Figure 5. Data Flow....................................................................................................................... 11 Figure 6. Voltage Input Filter Roll-off ............................................................................................ 12 Figure 7. Current Input Filter Roll-off............................................................................................. 12 Figure 8. Multi-Phase System ....................................................................................................... 13 Figure 9. CS5460 Register Diagram ............................................................................................. 14 Figure 10. Command and Data Word Timing ............................................................................... 19 Figure 11. Oscillator Connection................................................................................................... 27 Figure 12. System Calibration of Offset. ....................................................................................... 28 Figure 13. System Calibration of Gain. ......................................................................................... 28
LIST OF TABLES
Table 1. Specification with MCLK = 4.096 MHz, K = 1, and N = 4000.......................................... 10 Table 2. Internal Registers Default Value ..................................................................................... 20 Table 3. CPU Clock (and K) Restrictions ...................................................................................... 27
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1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = -40 C to +85 C; VA+, VD+ = +5 V 10%; VREFIN = 2.5 V; VA- = AGND; MCLK = 4.096 MHz, K = 1; N = 4000, OWR = 4.0 kHz.)(See Notes 1, 2, and 3)
Parameter Accuracy (Both Channels) Total Harmonic Distortion Common Mode Rejection Offset Drift (Without the High Pass Filter) Full Scale DC Calibration Range Input Sampling Rate Analog Inputs (Current Channel) Differential Input Voltage Range {(IIN+) - (IIN-)} (Gain = 10) (Gain = 50) (Gain = 10 or 50) (50, 60 Hz) (Gain = 10) (Gain = 50) (Note 5) (Gain = 10) (Gain = 50) (Gain = 10) (Gain = 50) (Note 1) (Note 1) {(VIN+) - (VIN-)} (50, 60 Hz) IC (Note 5) EII VOS FSE VIN IC EII 30 30 -0.25 5 (Note 1) (Note 1) VOS FSE 150 0.2 20 4 0.001 0.001 VA+ -70 250 0.01 0.01 k k Vrms Vrms %F.S. %F.S. mVrms V dB pF M Vrms %F.S. %F.S. IIN -0.25 150 30 5 25 VA+ -115 mVrms mVrms V dB pF pF (Note 4) DCLK = MCLK/K FSCR (DC, 50, 60 Hz) THD CMRR 74 80 25 5 DCLK/4 100 dB dB nV/C %F.S. Hz Symbol Min Typ Max Unit
Common Mode + Signal on IIN+ or IINInput Capacitance Effective Input Impedance
Crosstalk with Voltage Channel at Full Scale
Noise (Referred to Input) Accuracy (Current Channel) Bipolar Offset Error Full-Scale Error Analog Inputs (Voltage Channel) Differential Input Voltage Range Common Mode + Signal on VIN+ or VINCrosstalk with Current Channel at Full Scale Input Capacitance Effective Input Impedance Noise (Referred to Input) Accuracy (Voltage Channel) Bipolar Offset Error Full-Scale Error Notes: 1. Applies after system calibration
2. Specifications guaranteed by design, characterization, and/or test. 3. Analog signals are relative to VA- and digital signals to DGND unless otherwise noted. 4. The minimum FSCR is limited by the maximum allowed gain register value. 5. Effective Input Impedance (EII) varies with clock frequency (DCLK) and Input Capacitance (IC) EII = 1/(IC*DCLK/4)
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ANALOG CHARACTERISTICS (Continued)
Parameter Dynamic Characteristics Phase Compensation (Voltage Channel at 60 Hz) (Both Channels) -3 dB REFOUT (Output Current 1 A Source or Sink) (0.1 Hz to 512 kHz)
VR
Symbol
Min -2.4
Typ DCLK/1024 0.5 25 6 100 2.5 4 25 1.3 2.9 1.7 21 11.6 6.75 10 -
Max +2.5 2.6 60 10 2.6 25 -
Unit Hz Hz V ppm/C mV Vrms V pF nA mA mA mA mW mW mW W dB dB
High Rate Filter Output Word Rate High Pass Filter Pole Frequency Reference Output Output Voltage Temperature Coefficient Load Regulation Reference Input Input Voltage Range Input Capacitance Input CVF Current Power Supplies Power Supply Currents (Normal Mode) Output Noise Voltage
OWR
2.4 2.4 -
eN VREFIN
IA+ ID+ (VD+ = 5 V) ID+ (VD+ = 3 V)
PSCA PSCD PSCD PC
56 70 2.3
Power Consumption (Note 6)
Normal Mode (VD+ = 5 V) Normal Mode (VD+ = 3 V) Standby Sleep (50, 60 Hz) (Gain = 10) (Gain = 50)
Power Supply Rejection
PSRR PSRR PM
Power Monitor Thresholds Notes: 6. All outputs unloaded. All inputs CMOS level.
2.7
V
5 V DIGITAL CHARACTERISTICS (TA =
V) (See Notes 2 and 7) Parameter High-Level Input Voltage
-40 C to +85 C; VA+, VD+ = 5 V 10% VA-, DGND = 0 Symbol VIH Min 0.6 VD+ (VD+) - 0.5 0.8 VD+ (VD+) - 1.0 Typ 1 5 Max 0.8 1.5 0.2 VD+ 0.4 10 10 Unit V V V V
All Pins Except XIN and SCLK XIN SCLK All Pins Except XIN and SCLK XIN SCLK Iout = +5 mA Iout = -5 mA
Low-Level Input Voltage
VIL
High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance
VOH VOL Iin IOZ Cout
V V A A pF
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3 V DIGITAL CHARACTERISTICS (TA =
DGND = 0 V) (See Notes 2 and 7) Parameter High-Level Input Voltage All Pins Except XIN and SCLK XIN SCLK All Pins Except XIN and SCLK XIN SCLK Iout = +5 mA Iout = -5 mA Symbol VIH Min 0.6 VD+ (VD+) - 0.5 0.8 VD+ (VD+) - 1.0 Typ 1 5 Max 0.48 0.3 0.2 VD+ 0.4 10 10 Unit V V V V -40 C to +85 C; VA+ = 5 V 10%, VD+ = 3 V 10%; VA-,
Low-Level Input Voltage
VIL
High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance
VOH VOL Iin IOZ Cout
V V A A pF
Notes: 7. All measurements performed under static conditions.
ABSOLUTE MAXIMUM RATINGS (DGND = 0 V; See Note 8)
Parameter DC Power Supplies (Notes 9 and 10) Positive Digital Positive Analog Negative Analog (Note 11 and 12) Symbol VD+ VA+ VAIIN IOUT (Note 13) All Analog Pins All Digital Pins PDN VINA VIND TA Tstg Min -0.3 -0.3 +0.3 - 0.3 -0.3 -40 -65 Typ Max +6.0 +6.0 -6.0 10 25 500 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V V mA mA mW V V C C
Input Current, Any Pin Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: 8. All voltages with respect to ground. 9. VA+ and VA- must satisfy {(VA+) - (VA-)} < +6.0 V. 10. VD+ and VA- must satisfy {(VD+) - (VA-)} < +6.0 V. 11. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins. 12. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is 50 mA. 13. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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-40 C to +85 C; VA+ = 5.0 V 10%; VD+ = 3.0 V 10% or 5.0 V 10%; VA- = 0.0 V; Logic Levels: Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50pF)) Parameter Master Clock Frequency Master Clock Duty Cycle CPUCLK Duty Cycle Rise Times (Note 15) trise Any Digital Input Except SCLK (Note 16) SCLK Any Digital Output Any Digital Input Except SCLK (Note 16) SCLK Any Digital Output XTAL = 4.096 MHz (Note 17) Internal Gate Oscillator (Note 14) Symbol MCLK Min 2.5 40 40 200 200 50 50 100 100 50 50 60 Typ 4.096 Max 20 60 60 1.0 100 1.0 100 2 150 150 150 Unit MHz % % s s ns s s ns ms MHz ns ns ns ns ns ns ns ns ns
SWITCHING CHARACTERISTICS (TA =
Fall Times
tfall
Start-up Oscillator Start-up Time Serial Port Timing Serial Clock Frequency Serial Clock SDI Write Timing CS Enable to Valid Latch Clock Data Set-up Time Prior to SCLK Rising Data Hold Time After SCLK Rising SCLK Falling Prior to CS Disable SDO Read Timing CS Enable to Valid Latch Clock SCLK Falling to New Data Bit CS Rising to SDO Hi-Z t7 t8 t9 t3 t4 t5 t6 Pulse Width High Pulse Width Low SCLK t1 t2 tost
Notes: 14. Device parameters are specified with a 4.096 MHz clock, however, clocks between 3MHz to 20 MHz can be used. 15. If external MCLK is used, then its duty cycle must be between 45% and 55% to maintain this spec. 16. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF. 17. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source.
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CS
SDI
MSB t3
MSB - 1 t4 t5 t1 t2
LSB t6
SCLK
Figure 1. SDI Write Timing (Not to Scale)
CS t7 SDO MSB t8 SCLK MSB - 1 t1 t2 LSB t9
Figure 2. SDO Read Timing (Not to Scale)
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2. GENERAL DESCRIPTION
The CS5460 is a CMOS monolithic power measurement device with an energy computation engine. The CS5460 combines a programmable gain amplifier, two modulators, two high rate filters, system calibration, and power calculation functions to compute Energy, VRMS, IRMS, and Instantaneous Power. The CS5460 is designed for power meter applications and is optimized to interface to shunts or current transformers to measure current, and a resistive divider or transformer to measure voltage. To accommodate various input voltage levels due to shunts, the current channel includes a programmable gain amplifier (PGA) which allows the user to measure either 150mVRMS or 30mVRMS signals. The CS5460 includes two high-rate digital filters which output data at a (MCLK/K)/1024 output word rate (OWR). A high-pass filter in both channels can be enabled to remove the DC content from the input signal before the energy calculations are made.
N L 500 470 nF 500 100 F 0.1 F
To ease communication between the CS5460 and a micro-controller, the converter includes a simple three-wire serial interface which is SPITM and MicrowireTM compatible. The serial port also contains a Schmitt Trigger input on its serial clock (SCLK) to allow for slow rise time signals.
2.1 Theory of Operation
The CS5460 is designed to operate from a single +5 V supply or dual 2.5 V supplies, to provide a 30mVRMS or 150mVRMS range for the current channel and to provide a 150mVRMS range for the voltage channel. With single supply, the CS5460 is designed to accommodate common mode signals of -0.25V to VA+. Figure 3 illustrates the CS5460 connected to a service to measure power in a single-phase 2-wire system while operating in a single supply configuration. Figure 4 illustrates the CS5460 configured to measure power in a single-phase 3-wire system.
10 k 10 0.1 F 14 VA+
CS5460
5 k
3 VD+
9 CPV *
R2 R1
VIN+
PFMON CPUCLK XOUT
17 2 1
2.5 MHz to 20 MHz Optional Clock Source
10
VIN15 IIN-
XIN
24
RS
RESET CS SDI SDO SCLK INT EDIR EOUT DGND 4
RP I * CPI *
16
IIN+
12 VREFIN 11 VREFOUT VA13
19 7 23 6 5 20 22 21
Serial Data Interface
0.1 F
To Service
* Refer to Input Current Protection
Figure 3. Typical Connection Diagram (One-Phase 2-Wire)
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10 k L1 N L2 500 500 100 F 0.1 F 10 0.1 F 5 k
470 nF
14 VA+ CS5460
3 VD+
9 CPV * R1 R2 10 16 RPI * RS CPI *
VIN+
17 PFMON 2 CPUCLK 1 XOUT 24
2.5 MHz to 20 MHz Optional Clock Source
VINIIN+
XIN
RESET CS SDI IINSDO SCLK INT EDIR EOUT DGND 4
19 7 23 6 5 20 22
21
15
Serial Data Interface
12 VREFIN 11 VREFOUT 0.1 F
VA13
To Service
* Refer to Input Current Protection
Figure 4. Typical Connection Diagram (One-Phase 3-Wire)
2.2 Performing Measurements
The CS5460 performs measurements of instantaneous current, instantaneous voltage, instantaneous power, energy, RMS current, and RMS voltage. These measurements are output as 24-bit signed and unsigned data formats as a percentage of full scale. The flow of data to perform these calculations is shown in Figure 5. All of these measurements begin when a start conversion command is given. The energy and RMS registers are then updated every N conversions (or 1 computation cycle) where N is the content of the Cycle Count register. After the computation cycle has finished, the DRDY bit in the Status and Mask register is set. The INT pin will also become active if the DRDY bit is unmasked. Table 1 provides an example detailing the output linearity. A computation cycle is derived from the master clock and its frequency is (MCLK/K)/(1024*N). Instantaneous calculations are performed at a 4000 Hz rate where as, IRMS,
10
VRMS, and energy, are performed at a 1 Hz rate. Also, DRDY is set only after computation cycles are complete (i.e. there is no indicator flag to indicate when the instantaneous conversions are read; however, if the Cycle Count register were set to 1, all output calculations would be instantaneous and DRDY would indicate when instantaneous calculations were finished).
Energy
Vrms 2:1 0.1% of reading 24-bits
Irms 500:1 0.1% of reading
Range Max Input Linearity (After Calibration) Output word
1000:1 0.1% of reading
See Analog Characteristics
Table 1. Specification with MCLK = 4.096 MHz, K = 1, and N = 4000.
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V off *
V gn *
V*
VOLTAGE
DELAY REG
SINC 2
DELAY REG
FIR
HPF
+
x
x
SINC 2
N
V RMS *
APF Configuration Register * PC[3:0] Bits N x
TBC * x / 4096
P*
E* E out E dir
E to F
PULSE-RATE* CURRENT
SINC 4
FIR
HPF
+
x
x
SINC 2
N
I RMS *
APF
I off *
I gn *
I* * DENOTES REGISTER NAME
Figure 5. Data Flow.
2.2.1 Single Computation Cycle (C = 0)
Based on the information provided in the Cycle Count register, a single computation cycle is performed after the user transmits the single conversion cycle command. After the computations are complete, DRDY is set. Thirty-two SCLKs are then needed to acquire a calculation result. The first 8 SCLKs are used to clock in the command to determine which result register is to be read. The last 24 SCLKs are needed to read the desired calculation result register. After reading the data, the serial port returns to the command mode, where it waits for a new command to be issued.
choose to acquire only the calculations required for the application as DRDY rises and falls to indicate the availability of a new data. The RMS calculations require a Sinc2 operation prior to their square root operation. Therefore, the first output for each channel will be invalid (i.e. all RMS calculations are invalid in the single computation cycle routine and the first RMS calculations will be invalid in the continuous computation cycle). All energy calculations will be valid since energy calculations don't require this Sinc2 operation.
2.3 High Rate Digital Filters
The high rate filter on the voltage channel is implemented as a fixed sinc2 filter, compensated by a short length FIR. When the converter is driven with a 4.096 MHz clock (K=1), the filter has a magnitude response similar to that shown in Figure 6. Note that the filter's response scales with MCLK frequency and K. The current channel contains a sinc4 filter, compensated by a short length FIR. When the converter is driven with a 4.096 MHz clock (K=1) the composite filter response is given in Figure 7.
2.2.2 Multiple Computation Cycles (C = 1)
Based on the information provided in the Cycle Count register, continuous computation cycles are repeatedly performed on the voltage and current cycles. Computation cycles cannot be started/stopped on a per channel basis. After each computation cycle is completed, DRDY is set. Thirty-two SCLKs are then needed to read a register. The first 8 SCLKs are used to clock in the command to determine which results register is to be read. The last 24 SCLKs are needed to read the calculation result. While in this mode, the user may
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0.5
0.0
Gain (dB)
-0.5
-1.0
meter (Figure 3) is required to generate 500 impulses/KWH at Ib = 20 ARMS and V = 230 VRMS. Assume that the maximum current is Imax = 100 ARMS and the maximum voltage is Vmax= 300 VRMS. To utilize the full dynamic range of the CS5460, the sensor gains can be calculated as:
150mV RMS 1k v = ---------------------------- = ----------V max 2000
0 200 400 600 800 1000 1200 1400 1600 1800 2000
-1.5
-2.0
-2.5 Frequency (Hertz)
30mV RMS k i = ------------------------- = 300 I max
Figure 6. Voltage Input Filter Roll-off
0.5 0 -0.5
where kv and ki are the sensor gains for the voltage and current, respectively. The CS5460 is assumed to be in the 30 mVRMS range to allow for the use of a shunt resistor. The average Impulse Rate, IR, at the rated inputs is:
Gain (dB)
-1 -1.5 -2 -2.5 0
200
400
600
800
1000 1200
1400 1600
1800 2000
500 impulses 1KW 1H 0.639 impulses R = ------------------------------- ( I b V ) ----------------- ------------- ---------------------------------- 1000W 3600s KWH s
Frequency (Hertz)
Figure 7. Current Input Filter Roll-off
2.4 Pulse-Rate Output
As an alternative to reading the energy through the serial port, the EOUT and EDIR pins provide a simple interface with which signed energy can be accumulated. Each EOUT pulse represents a predetermined magnitude of energy. The accompanying EDIR level represents the sign of the energy. With MCLK = 4.096 MHz, K = 1, and both ADC inputs at their maximum DC values, the pulses will have a frequency equal to that in the pulse rate register. The following example illustrates how to calculate the pulse-rate register contents for a given meter design. Suppose that a single two-phase power
Since the pulse-rate register is defined in terms of full-scale DC (0.25 V for the voltage channel and 0.05 V for the current channel in this case), IR will need to be scaled before being placed in the pulse-rate register. Define a voltage ratio, Rv, and a current ratio, Ri, as:
0.25 Volt R v = ---------------------k v V Volt
0.05 Volt R i = ---------------------k i I b Amp
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Therefore, the pulse rate register is programmed to be :
PR = IR x Rv x R i 11.574 Hz = 370 or 0x172
mum frequency is therefore MCLK/K/8. A timing diagram for a multi-phase system is shown in Figure 8.
Phase - 00 t Phase - 01
To improve the accuracy, either gain register can be programmed to correct for the round-off error in PR. This value would be calculated as
PR Ign or Vgn = ---------------------- 1.001 = 0x401067 -5 370 x 2
Phase - 10
t Phase - 11
t
Pulse-Rate Register Period 8
=
N MCLK/K
for Integer N
Figure 8. Multi-Phase System
To allow for a simpler interface in a multi-phase system, the EOUT and EDIR pins can be connected together and used in a wired-or configuration. The parts must be driven with the same clock and programmed with different phases (PH[1:0] in the Configuration register). The pulse width and the pulse separation is an integer multiple of system clocks (approximately equal to 1/8 of the period of the contents of the pulse-rate register). The maxi-
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3. SERIAL PORT OVERVIEW
The CS5460's serial port incorporates a state machine with transmit/receive buffers. The state machine interprets 8 bit command words on the rising edge of SCLK. Upon decoding of the command word the state machine performs the requested command or prepares for a data transfer of the addressed register. Request for a read requires an internal register transfer to the transmit buffer, while a write waits until the completion of 24 SCLKs before performing a transfer. The internal registers are used to control the ADC's functions. All registers are 24-bits in length. Figure 9 depicts the internal registers available to the user. After system initialization or reset, the serial port state machine is initialized into command mode where it waits to receive a valid command (the first 8-bits clocked into the serial port). Upon receiving and decoding a valid command word the state machine instructs the converter to either perform a system operation, or transfer data to or from an internal register. The Command Word section can be used to decode all valid commands. The state machine decodes the command word as it is received. The serial port enters data transfer mode if the MSB of the command word is logic 0 (B7 = 0). In data transfer mode, the internal registers are read from or written to. Command words instructing a register write must be followed by 24 bits of data. For instance, to write the configuration register, the user would transmit the command (0x40) to initiate the write. The ADC would then acquire the serial data input from the (SDI) pin when the user pulses the serial clock (SCLK) 24 times. Once the data is received the state machine would write the data to the configuration register and return to the command mode. Command words instructing a register read may be terminated at 8-bit boundaries (e.g., read transfers may be 8, 16, or 24 bits in length). Also data register reads allow "command chaining". For example, a command word instructs the state machine to read a signed output register. After the user pulses SCLK for 16-bits of data, a write command word (e.g., to clear the status register) may be pulsed on to the SDI line at the same time the remaining 8-bits of data are pulsed from the SDO line.
Current Channel Voltage Channel
Offset Register (1 x 24)
Gain Register (1 x 24)
Signed Output Registers (4 x 24) (I, V, P, E)
Offset Register (1 x 24)
Gain Register (1 x 24) Unsigned Output Registers (2 x 24) (I RMS, V RMS)
Pulse-Rate Register (1 x 24)
Cycle-Counter Register (1 x 24) Receive Buffer 24-Bit Serial Interface
Transmit Buffer
SDI CS
SDO
Timebase Register (1 x 24)
Status Register (1 x 24)
Configuration Register (1 x 24)
Mask Register (1 x 24)
Command Word State Machine
SCLK INT
Figure 9. CS5460 Register Diagram
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3.1 Command Word (Write Only)
All command words are always 1 byte in length. Commands that write to a register initiate 3 bytes of register data. Commands that read from registers must be followed by 1, 2, or 3 bytes of register read data. Commands that read data can be chained with other commands (e.g., while reading data, a new command can be sent to SDI which can execute before the original read is completed). This allows for "chaining" commands.
3.1.1 Start Conversions
B7 1 B6 1 B5 1 B4 0 B3 C B2 0 B1 0 B0 0
This command indicates to the state machine to begin acquiring measurements and calculating results. The device has two modes of acquisition. C Modes of measurement 0 = Perform a single computation cycle 1 = Perform continuous computation cycles
3.1.2 SYNC0 Command
B7 1 B6 1 B5 1 B4 1 B3 1 B2 1 B1 1 B0 0
This command is the end of the serial port re-initialization sequence. The command can also be used as a NOP command. The serial port is resynchronized to byte boundaries by sending three or more consecutive SYNC1 commands followed by a SYNC0 command.
3.1.3 SYNC1 Command
B7 1 B6 1 B5 1 B4 1 B3 1 B2 1 B1 1 B0 1
This command is part of the serial port re-initialization sequence. The command can also serve as a NOP command, but no more than three consecutive bytes should be transmitted.
3.1.4 Power-up/Halt Control
B7 1 B6 0 B5 1 B4 0 B3 0 B2 0 B1 0 B0 0
If the device is powered-down, this command will power-up the device. When powered-on, no computations will be running. If the part is already powered-on, all computations will be halted.
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3.1.5 Power-down Control
B7 1 B6 0 B5 0 B4 S1 B3 S0 B2 0 B1 0 B0 0
The device has two power-down modes to conserve power. If the chip is put in stand-by mode all circuitry except the clock generator is turned off. S1,S0 Power-down mode 00 = Reserved 01 = Halt and enter stand-by power saving mode. This mode allows quick power-on time 10 = Halt and enter sleep power saving mode. This mode requires a slow power-on time 11 = Reserved
3.1.6 Calibration Control
B7 1 B6 1 B5 0 B4 Cv B3 Ci B2 0 B1 GC B0 OC
The device has the capability of performing a system offset and gain calibration. The user must supply the proper inputs to the device before proceeding with the calibration cycle. Cv,Ci Designates calibration channel 00 = Not allowed 01 = Calibrate the current channel 10 = Calibrate the voltage channel 11 = Calibrate voltage and current channel simultaneously Designates gain calibration 0 = Normal operation 1 = Perform gain calibration Designates offset calibration 0 = Normal operation 1 = Perform offset calibration
GC
OC
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3.1.7 Register Read/Write Command
B7 0 B6 W/R B5 RA4 B4 RA3 B3 RA2 B2 RA1 B1 RA0 B0 0
This command informs the state machine that a register access is required. On reads the addressed register is loaded into the output buffer and clocked out by SCLK. On writes the data is clocked into the input buffer and transferred to the addressed register on the 24th SCLK. W/R Write/Read control 0 = Read register 1 = Write register Register address bits. Binary encoded 0 to 31. All registers are 24 bits in length. Address 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 . . 10111 11000 11001 11010 11011 11100 . . 11111 Name Config Ioff Ign Voff Vgn Cycle Count Pulse-Rate I V P E IRMS VRMS TBC Test Status Res Description Configuration Register Current offset calibration Current gain calibration Voltage offset calibration Voltage gain calibration Number of conversions to integrate over (N) Used to calibrate/scale the energy to frequency output Last current value Last voltage value Last Power value Total energy value of last cycle RMS current value of last cycle RMS voltage value of last cycle Timebase Calibration Internal Use only Status register Reserved
RA[4:0]
Res Test Test Mask Test Res
Reserved Internal Use only Internal Use Only Interrupt mask register Internal Use Only Reserved
Res
Reserved
These Registers are for Internal Use only and should not be written to. Accessing these registers will NOT generate an "Invalid Command" (IC) bit in the Status Register.
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3.2 Serial Port Interface
The CS5460's serial interface consists of four control lines: CS, SDI, SDO, and SCLK. CS, Chip Select, is the control line which enables access to the serial port. If the CS pin is tied to logic 0, the port can function as a three wire interface. SDI, Serial Data In, is the data signal used to transfer data to the converters. SDO, Serial Data Out, is the data signal used to transfer output data from the converters. The SDO output will be held at high impedance any time CS is at logic 1. Figure 10 illustrates the serial sequence necessary to write to, or read from the serial port's buffers. SCLK, Serial Clock, is the serial bit-clock which controls the shifting of data to or from the ADC's serial port. The CS pin must be held at logic 0 before SCLK transitions can be recognized by the port logic. To accommodate opto-isolators SCLK is designed with a Schmitt-trigger input to allow an opto-isolator with slower rise and fall times to directly drive the pin. Additionally, SDO is capable of sinking or sourcing up to 5 mA to directly drive an opto-isolator LED. SDO will have less than a 400 mV loss in the drive voltage when sinking or sourcing 5 mA. As shown in Figure 10 a transfer of data is always initiated by sending the appropriate 8-bit command (MSB first) to the serial port (SDI pin). It is important to note that some commands use information from the cycle-counter and configuration registers to perform the function. For those commands it is important that the correct information is written to those registers first. When a command involves a write operation the serial port will continue to clock in the data bits (MSB first) on the SDI pin for the next 24 SCLK cycles. When a read command is initiated the serial port will start transferring register content bit serial (MSB first) on the SDO pin for the next 8, 16, or 24 SCLK cycles depending on the command issued. The micro-controller is allowed to send a new command while reading register data. The new command will be acted upon immediately and could possibly terminate the register read. During the read cycle, the SYNC0 command (NOP) should be strobed on the SDI port while clocking the data from the SDO port.
3.3 Serial Port Initialization
The serial port is initialized to the command mode whenever a reset is performed or when the port initialization sequence is completed. The port initialization sequence involves clocking 3 (or more) SYNC1 command bytes (0xFF) followed by SYNC0 command byte (0xFE). This sequence places the chip in the command mode where it waits until a valid command is received.
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CS
SCLK MSB SDI Command Time 8 SCLKs Data Time 24 SCLKs LSB MSB LSB
Write Cycle
CS
SCLK MSB SDI
Command Time 8 SCLKs
LSB
MSB
LSB
SDO Data Time 24 SCLKs
Read Cycle Figure 10. Command and Data Word Timing
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3.4 System Initialization
A software or hardware reset can be initiated at any time. The software reset is initiated by writing a logic 1 to the RS (Reset System) bit in the configuration register, which automatically returns to logic 0 after reset. At the end of the 32nd SCLK (i.e., 8 bit command word and 24 bit data word) internal synchronization delays the loading of the configuration register by 3 or 4 DCLK (MCLK/K). Then the reset circuit initiates the reset routine on the 1st falling edge of MCLK. A hardware reset is initiated when the RESET pin is forced low with a minimum pulse width of 50 ns. The RESET signal is asynchronous requiring no MCLKs for the part to detect and store a reset event. Once the RESET pin is inactive the internal reset circuitry remains active for 5 MCLK cycles to insure resetting the synchronous circuitry in the device. The modulators are held in reset for 12 MCLK cycles after RESET becomes inactive. The internal registers (some of which drive output pins) will be reset to their default values on the first MCLK received after detecting a reset event (see Table 2). After a reset, the on-chip registers are initialized to the following states and the converter is placed in the command mode where it waits for a valid command.
Configuration Register: Offset Register: Gain Registers Pulse-Rate Register: Cycle-Counter Register: Timebase Register: Status Register: Mask Register Signed Registers Unsigned Registers
0x000001 0x000000 0x400000 0x0FA000 0x000FA0 0x800000 0x000001 0x000000 0x000000 0x000000
Table 2. Internal Registers Default Value
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4. REGISTER DESCRIPTION
Notes: * "RA[4:0]" => register address bits in the Register Read/Write Command word ** "default" => bit status after reset
4.1 Configuration Register
Address: RA[4:0]* = 0x00
23 PC3 15 EWA 7 RS 22 PC2 14 PH1 6 VHPF 21 PC1 13 PH0 5 IHPF 20 PC0 12 SI1 4 iCPU 19 0 11 SI0 3 K3 18 0 10 EOD 2 K2 17 0 9 DL1 1 K1 16 Gi 8 DL0 0 K0
Default** = 0x000001 K[3:0] Clock divider. A 4 bit binary number ranging from 0 to 15 used to divide the value of MCLK to generate the internal clock DCLK. The internal clock frequency of DCLK = MCLK/K. Valid values are 1,2, and 4. 0001 = divide by 1 (default) 0010 = divide by 2 0100 = divide by 4 Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals are sampled, the logic driven by CPUCLK should not be active during the sample edge. 0 = normal operation (default) 1 = minimize noise when CPUCLK is driving rising edge logic Control the use of the High Pass Filter on the Current Channel. 0 = High-pass filter is disabled. If VHPF is set, use all-pass filter. Otherwise, no filter is used. (default) 1 = High-pass filter is enabled. Control the use of the High Pass Filter on the voltage Channel. 0 = High-pass filter is disabled. If IHPF is set, use all-pass filter. Otherwise, no filter is used. (default) 1 = High-pass filter enabled Start a chip reset cycle when set 1. The reset cycle lasts for less than 10 XIN cycles. The bit is automatically returned to 0 by the reset cycle. When EOD = 1, EDIR becomes a user defined pin. DL0 sets the value of the EDIR pin. Default = '0' When EOD = 1, EOUT becomes a user defined pin. DL1 sets the value of the EOUT pin. Default = '0' Allows the EOUT and EDIR pins to be controlled by the DL0 and DL1 bits. EOUT and EDIR can also be accessed using the status register. 0 = Normal operation of the EOUT and EDIR pins. (default) 1 = DL0 and DL1 bits control the EOUT and EDIR pins. Soft interrupt configuration. Select the desired pin behavior for indication of an interrupt. 00 = active low level (default)
iCPU
IHPF
VHPF
RS DL0 DL1 EOD
SI[1:0]
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01 = active high level 10 = falling edge (INT is normally high) 11 = rising edge (INT is normally low) PH[1:0] Set the phase of the EOUT and EDIR output pin pulse. The EOUT and EDIR pins, on different phases, can be wire-ORed together as a simple way of summing the frequency of different parts. 00 = phase 0 (default) 01 = phase 1 10 = phase 2 11 = phase 3 Allows the output pins of EOUT and EDIR of multiple chips to be connected in a wire-AND, using an external pull-up device. 0 = normal outputs (default) 1 = only the pull-down device of the EOUT and EDIR pins are active Sets the gain of the current PGA 0 = gain is 10 (default) 1 = gain is 50 Reserved. These bits must be set to zero. Phase compensation. A 2's complement number used to set the delay in the voltage channel. The bigger the number, the greater the delay in the voltage. The phase adjustment range is about -2.4 to +2.5 degrees at 60Hz. Each step is about 0.34 degrees at 60Hz. 0000 = Zero degrees phase delay (default)
EWA
Gi
Res PC[3:0]
4.2 Current Offset Register and Voltage Offset Register
Address: RA[4:0]* = 0x01 (Current Offset Register) RA[4:0]* = 0x03 (Voltage Offset Register)
LSB 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24
MSB SIGN
Default** = 0.000 The Offset Registers are initialized to zero on reset, allowing the device to function and perform measurements. The register is loaded after one cycle with the system offset when the proper input is applied and the Calibration Command is received. The register may be read and stored so the register may be restored with the desired system offset compensation. The value is in the range 1/2 full scale.
4.3 Current Gain Register and Voltage Gain Register
Address: RA[4:0]* = 0x02 (Current Gain Register) RA[4:0]* = 0x04 (Voltage Gain Register)
LSB 20 2-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 2-22
MSB 21
Default** = 1.000 The Gain Registers are initialized to 1.0 on reset, allowing the device to function and perform measurements. The register is loaded after one cycle with the system gain when the proper input is applied and the Calibration Command is received. The register may be read and stored so the register may be restored with the desired system offset compensation. The value is in the range 0.0 Gain < 4.0. 22 DS279PP5
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4.4 Cycle Count Register
Address: RA[4:0]* = 0x05
MSB 2
23
LSB 2
22
2
21
2
20
2
19
2
18
2
17
2
16
.....
26
2
5
2
4
2
3
2
2
2
1
20
Default** = 4000 The Cycle Count Register determines the length of an energy and RMS conversion. A conversion cycle is derived from (MCLK/K)/(1024N) where MCLK is master clock, K is clock divider, and N is cycle count. N must be greater than 10 for IRMS, VRMS and energy calculations to be performed.
4.5 Pulse-Rate Register
Address: RA[4:0]* = 0x06
MSB 218 2
17
LSB 2
16
2
15
2
14
2
13
2
12
2
11
.....
21
2
0
2
-1
2
-2
2
-3
2
-4
2-5
Default** = 32000.00Hz The Pulse-Rate Register determines the frequency of the train of pulses output on the EOUT pin. Each EOUT pulse represents a predetermined magnitude of energy.The register's smallest valid value is 2-4 but can be in 2-5 increments.
4.6 I,V,P,E Signed Output Register Results
Address: RA[4:0]* = 0x07 - 0x0A
MSB SIGN LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Access: Read Only The Signed Registers contain the last value of the measured results of I, V, P, and E. The results are in the range of -1.0 I, V, P, E < 1.0. The value is represented in two's complement notation, with the binary point place to the right of the MSB (which is the sign bit). I, V, P, and E are output results registers which contain signed values.
4.7 IRMS, VRMS Unsigned Output Register Results
Address: RA[4:0]* = 0x0B - 0x0C
MSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 LSB 2-24
Access: Read Only The Unsigned Registers contain the last value of the calculated results of IRMS and VRMS. The results are in the range of 0.0 IRMS,VRMS < 1.0. The value is represented in binary notation, with the binary point place to the left of the MSB. IRMS and VRMS are output result registers which contain unsigned values.
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4.8 Timebase Calibration
Address: RA[4:0]* = 0x0D
MSB 2
0
LSB 2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2-17
2
-18
2
-19
2
-20
2
-21
2
-22
2-23
Default** = 1.000 The Timebase Register is initialized to 1.0 on reset, allowing the device to function and perform computations. The register is user loaded with the clock frequency error to compensate for a gain error caused by the crystal/oscillator tolerance. The value is in the range 0.0 TBC < 2.0.
4.9 Status Register and Mask Register
Address: RA[4:0]* = 0x0F (Status Register) RA[4:0]* = 0x1A (Mask Register)
22 EOUT 14 IROR 6 Res 21 EDIR 13 VROR 5 WDT 20 Res 12 EOR 4 VOD 19 MATH 11 EOOR 3 IOD 18 Res 10 Res 2 LSD 17 IOR 9 Res 1 0 16 VOR 8 Res 0 IC
23 DRDY 15 PWOR 7 Res
Default** = 0x000001 (Status Register) 0x000000 (Mask Register) The Status Register indicates the condition of the chip. In normal operation writing a '1' to a bit will cause the bit to go to the '0' state. Writing a '0' to a bit will maintain the status bit in its current state. With this feature the user can simply write back the status register to clear the bits that have been seen, without concern of clearing any newly set bits. Even if a status bit is masked to prevent the interrupt, the status bit will still be set in the status register so the user can poll the status. The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the mask register will allow the corresponding bit in the status register to activate the INT pin when the status bit becomes active. IC Invalid Command. Normally logic 1. Set to logic 0 when the part is given an invalid command. Can be deactivated only by sending a port initialization sequence to the serial port. When writing to status register this bit is ignored. Low Supply detect. Set when the PFMON pin falls below 2.5 volts with respect to the VA- pin. Modulator oscillation detect on the current channel. Set when the modulator oscillates due to an input above Full Scale. Modulator oscillation detect on the voltage channel. Set when the modulator oscillates due to an input above Full Scale. Watch-Dog Timer. Set when there has been no reading of the Energy register for more than 5 seconds. (MCLK = 4.096 MHz, K = 1) To clear this bit, first read the Energy register, then write to the status register with this bit set to logic '1'. EOUT energy/current summing register went out of range. This can be caused by having an output rate that is too small for the power being measured. The problem can be corrected by specifying a higher frequency in the pulse-rate register. DS279PP5
LSD IOD VOD WDT
EOOR
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EOR VROR IROR PWOR VOR IOR MATH EDIR EOUT Energy Out of Range. Set when the calibrated energy value is too large or too small to fit in the output word. RMS Voltage Out of Range. Set when the calibrated RMS voltage value is too large to fit in the output word. RMS Current Out of Range. Set when the calibrated RMS current value is too large to fit in the output word. Power Calculation Out of Range. Voltage Out of Range. Set when the calibrated voltage value is too large or too small to fit in the output word. Current Out of Range. Set when the calibrated current value is too large or too small to fit in the output word. General computation error (e.g., divide by 0) Set when sum of energy is less than zero. Set or cleared at the same time as EOUT. Indicates that the energy limit has been reached for the energy to frequency conversion, and a pulse train will be generated on the EOUT pin (if enabled). This bit is cleared automatically when the energy rate drops below the level that produces a 4 KHz EOUT pin rate. The bit can also be cleared by writing to the status register. This status bit is set with a maximum frequency of 4 KHz (when MCLK/K is 4.096 MHz). Data Ready. Set at the end of a calibration or conversion cycle.
DRDY
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5. FUNCTIONAL DESCRIPTION 5.1 Interrupt and Watchdog Timer 5.1.1 Interrupt
The INT pin is used to indicate that an event has taken place in the converter that needs attention. These events inform the system about operation conditions and internal error conditions. The INT signal is created by combining the Status register with the Mask register. Whenever a bit in the Status register becomes active, and the corresponding bit in the Mask register is a logic 1, the INT signal becomes active. The interrupt condition is cleared when the bits of the status register are returned to their inactive state. Interrupt Handler Routine: Step H0 - Read the Status register. Step H1 - Disable all interrupts. Step H2 - Branch to the proper interrupt service routine. Step H3 - Clear the Status register by writing back the value read in step H0. Step H4 - Re-enable interrupts. Step H5 - Return from interrupt service routine. This handshaking procedure insures that any new interrupts activated between steps H0 and H3 are not lost (cleared) by step H3.
5.1.1.3 INT Active State
The behavior of the INT pin is controlled by the SI1 and SI0 bits of the configuration register. The pin can be active low (default), active high, active on a return to logic 0 (rising edge), or activate on a return to logic 1 (falling edge).
5.1.1.1 Clearing the Status Register
Unlike the other registers, the bits in the Status register can only be cleared (set to logic 0). When a word is written to the Status register, any 1s in the word will cause the corresponding bits in the Status register to be cleared. The other bits of the status register remain unchanged. This allows the clearing of particular bits in the register without having to know the state of the other bits. This mechanism is designed to facilitate handshaking and to minimize the risk of losing events that haven't been processed yet.
5.1.1.4 Exceptions
The IC (Invalid Command) bit of the Status register can only be cleared by performing the port initialization sequence. This is also the only Status register bit that is active low. To properly clear the WDT (WatchDog Timer) bit of the Status register, one must first read the Energy register, then clear the bit in the status register.
5.1.1.2 Typical use of the INT pin
The steps below show how interrupts can be handled. Initialization: Step I0 - All Status bits are cleared by writing FFFFFF (Hex) into the Status register. Step I1 - The conditional bits which will be used to generate interrupts are then written to logic 1 in the Mask register. Step I3 - Enable interrupts.
5.1.2 Watch Dog Timer
The Watch Dog Timer (WDT) is provided as means of alerting the system that there is a potential breakdown in communication with the micro-controller. By allowing the WDT to cause an interrupt, a controller can be brought back, from some unknown code space, into the proper code for processing the data created by the converter. The time-out is preprogrammed to approximately 5 seconds. The countdown restarts each time the Energy register is read. Under typical situations, the EnerDS279PP5
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gy register is read every second. As a result, the WDT will not time out. Other applications, that want to use the watchdog timer, will need to ensure that the Energy register is read at least once in every 5 second span. The CS5460 can be driven by a clock ranging from 2.5 to 20 MHz Table 2 shows the clock divide value K (default = 1) that the CS5460 needs to be programmed with for normal operation.
K CLK (min) MHz 2.5 5 10 CLK (max) MHz 5 10 20
5.2 Oscillator Characteristics
XIN and XOUT are the input and output, respectively, of an inverting amplifier to provide oscillation and can be configured as an on-chip oscillator, as shown in Figure 11. The oscillator circuit is designed to work with a quartz crystal or a ceramic resonator. To reduce circuit cost two load capacitors C1 are integrated in the device, one between XIN and DGND, one between XOUT and DGND. Lead lengths should be minimized to reduce stray capacitance. With these load capacitors the oscillator circuit is capable of oscillation up to 20 MHz. To drive the device from an external clock source, XOUT should be left unconnected while XIN is driven by the external circuitry. There is an amplifier between XIN and the digital section which provides CMOS level signals. This amplifier works with sinusoidal inputs so there are no problems with slow edge times.
1 2 4
Table 3. CPU Clock (and K) Restrictions
5.3 Analog Inputs
The CS5460 accommodates a full scale range of 150 mVRMS on both input channels. System calibration can be used to increase or decrease the full scale span of the converter as long as the calibration register values stay within the limits specified. See the Calibration section for more details. The current input channel has an input range of 30 mVRMS when the internal x50 gain stage is enabled. This signal range is designed to handle low level signals from a shunt sensor.
XOUT C1
Oscillator Circuit
XIN C1
DGND
C1 = 22 pF
Figure 11. Oscillator Connection
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5.4 Voltage Reference
The CS5460 is specified for operation with a +2.5 V reference between the VREFIN and VA- pins. The converter includes an internal 2.5 V reference (60 ppm/C drift) that can be used by connecting the VREFOUT pin to the VREFIN pin of the device. If higher accuracy/stability is required, an external reference can be used. calibration, any initial offset and gain errors in the internal circuitry of the chip will remain.
5.5.1 System Calibration
For the system calibration functions, the user must supply the converters calibration signals which represent ground and full scale. When a system offset calibration is performed, a ground reference signal must be applied to the converters. Figure 12 illustrates system offset calibration. As shown in Figure 13, the user must input a signal representing the positive full scale point to perform a system gain calibration. In either case, the calibration signals must be within the specified calibration limits for each specific calibration step (refer to Full Scale DC Calibration Range).
5.5 Performing Calibrations
The CS5460 offers two DC calibration modes: system offset and system gain. For system calibration the user must supply the converter calibration signals which represent ground and full scale. The user must provide the positive full scale point to perform a system gain calibration and a ground referenced signal when a system offset is performed. The offset and gain signals must be within the specified calibration limits for each specific calibration step and channel. Since each converter channel has its own offset and gain register associated with it, system offset, or system gain can be performed on either channel without the calibration results from one channel corrupting the other. The Cycle Count register N, determines the number of conversions averaged to obtain the calibration results. The larger N, the higher the accuracy of the calibration results. Once a calibration cycle is complete, DRDY is set and the results are stored in either the gain or offset register. Note that if additional calibrations are performed, the latest calibration results will replace the effects from the previous calibration. In any event, offset and gain calibration steps take one cycle each to complete. After the part is reset, the device is functional and can perform measurements without being calibrated. The converters will utilize the initialized values of the on-chip registers (Gain = 1.0, Offset = 0.0) to calculate power information. Although the device can be used without performing an offset or gain
External Connections + AIN+ 0V + CM + AINXGAIN +
Figure 12. System Calibration of Offset.
External Connections + AIN+ Full Scale + CM + -
+ XGAIN -
AIN-
Figure 13. System Calibration of Gain.
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5.5.2 Calibration Tips
To minimize digital noise near the device, the user should wait for each calibration step to be completed before reading or writing to the serial port. After a calibration is performed, the offset and gain register contents can be read by the system micro-controller and recorded in memory. The same calibration words can be uploaded into the offset and gain registers of the converters when power is first applied to the system, or when the gain range on the current channel is changed. An offset calibration must be performed before a gain calibration. Each gain calibration depends on the zero calibration point obtained from the offset calibration. The offset and gain calibration steps each take one conversion cycle to complete. At the end of the calibration step, DRDY is set to indicate that the calibration is complete. Capacitors CPV and CPI should be included to provide for attenuation of high-frequency noise that may be coupled into the input lines. In differential input configurations, such a capacitor should be added to the VIN- and IIN- pins in addition to the VIN+ and IIN+ pins. Values for RPV/I and CPV/I must be chosen with the approximate input lowpass cutoff frequency in mind. In general, the cutoff frequency should not be less than 10 times the roll-off frequencies of the internal voltage/current channel filters (see Figure 6 and Figure 7). From these figures we see that the internal voltage channel roll-off is at ~1400Hz while the current channel roll-off is at ~1600Hz. If the cutoff frequency of the external protection is much less than 10x these values (14000Hz and 16000Hz), then some of the harmonic content in the power signal may start to get attenuated by this input filtering, which is undesirable. The exact values of RPV/I and CPV/I must be calculated for each particular application. The primary goal is to make sure that the input pins never receive transient input currents greater than 100mA. Also, they should never be exposed to DC currents greater than 10mA. The user-supplied protection resistors RPV and RPI will limit the current that comes into the pins in over-voltage--where the internal protection diodes turn on inside the CS5460. For example, suppose that the value for RPI (on the current channel input) was chosen to be 500 Ohms. Then we know that the current channel can withstand brief voltage spikes of up to ~50V (referenced to GND) without damage to the part. This is because 50V / 500Ohm = 100mA. We can also say that the pin can withstand a common mode DC voltage of up to 5V. When computing appropriate values for RPV/I, the differential input impedance of the CS5460's voltage channel and current channel should also be considered. This is especially true for the current channel, which has a lower differential input im-
5.6 Input Current Protection
In Figure 3 and Figure 4, note the series resistor RPI which is connected to the IIN+ input pin. This resistor is used to provide current-limit protection for the current-channel input pin in the event of a power surge or lightening surge. The voltage/current-channel inputs have surge-current limits of 100mA. This applies to brief voltage/current spikes (<500 msec). The limit is 10mA for DC input overload situations. The VIN+ pin does not need a protection resistor for the configurations shown in Figure 3 and Figure 4. This is because a resistive voltage-divider is used as the sensor, and so series resistance is already provided to the VIN+ input pin. (If it was installed, it would be called RPV). If the negative sides of the CS5460 input channels are not grounded (i.e., if VIN- and IIN- are connected in a differential configuration) then it is appropriate to put protection resistors on these inputs as well.
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pedance than the voltage channel. These impedance specs are given at the beginning of this data sheet (see the specification titled "Effective Input Impedance" for the voltage and current channels). For example, the differential input impedance in the current channel is spec'd to be 30 kOhm. As the user increases the value of RPI to provide for more and more common-mode surge protection, the voltage drop across the external protection resistor increases, and it divides the input signal down more and more. This in turn reduces the dynamic range of the signals that are ultimately presented to the CS5460's inputs. As an example, suppose that the user creates a current-sensor configuration that provides a differential voltage of 150mV (RMS) across shunt resistor RS at maximum line-current level. However, the user has set RPI to 500 Ohms. This means that when there is 150mV across the shunt resistor (RS), the voltage across the IIN+ and IIN- inputs is actually 150mV * [ 30K / (500 + 30K)] = ~148mV (RMS). We see that this has decreased the maximum signal input level. To avoid this voltage division, the user should first consider the input protection that is going to be necessary, and then calculate the sensor gains such that the drop across the protection resistors is taken into account. Typical values for these components are RPI = 500 Ohm, CPI = 0.02uF, CPV = 0.002uF and if necessary, RPV = 5 KOhm.
5.7 PCB Layout
The CS5460 should be placed entirely over an analog ground plane with both the VA- and DGND pins of the device connected to the analog plane. Place the analog-digital plane split immediately adjacent to the digital portion of the chip.
Note: See the CDB5460 data sheet for suggested layout details and Applications Note 18 for more detailed layout guidelines. Before layout, please call for our Free Schematic Review Service.
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DS279PP5
CS5460
6. PIN DESCRIPTION
Crystal Out CPU Clock Output Positive Digital Supply Digital Ground Serial Clock Input Serial Data Output Chip Select No Connect Differential Voltage Input Differential Voltage Input Voltage Reference Output Voltage Reference Input XOUT CPUCLK VD+ DGND SCLK SDO CS NC VIN+ VINVREFOUT VREFIN
1 2 3
4
24 23 22
21
XIN SDI EDIR EOUT INT RESET NC PFMON IIN+ IINVA+ VA-
Crystal In Serial Data Input Energy Direction Indicator Energy Output Interrupt Reset No Connect Power Fail Monitor Differential Current Input Differential Current Input Positive Analog Supply Analog Ground
5 6
7
20 19
18
8 9 10 11 12
17 16 15 14 13
Clock Generator Crystal Out Crystal In CPU Clock Output SCLK
1,24 XOUT, XIN - A gate inside the chip is connected to these pins and can be used with a crystal to provide the system clock for the device. Alternatively, an external (CMOS compatible clock) can be supplied into XIN pin to provide the system clock for the device. CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.
2
Control Pins and Serial Data I/O
5 Serial Clock Input - A clock signal on this pin determines the input and output rate of the data for the SDI and SDO pins respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin will recognize clocks only when CS is low. Serial Data Output - SDO is the output pin of the serial data port. Its output will be in a high impedance state when CS is high. Chip Select - When active low, the port will recognize SCLK. An active high on this pins puts the SDO pin in a high impedance state. CS should be changed when SCLK is low. Interrupt - When INT goes low it signals that an enabled event has occurred. INT is cleared (logic 1) by writing the appropriate command to the CS5460. Energy Output - The energy output pin output a fixed-width pulse rate output with a rate (programmable) proportional to energy. The energy direction indicator indicates if the measured energy is negative. Energy Direction Indicator - Serial Data Input - SDI is the input pin of the serial data port. Data will be input at a rate determined by SCLK.
SDO CS INT EOUT EDIR SDI
6 7 20 21 22 23
Measurement and Reference Input Differential Voltage Inputs Voltage Reference Output Voltage Reference Input DS279PP5
9,10 11 12 VIN+, VIN- - Differential analog input pins for voltage channel. VREFOUT - The on-chip voltage reference is output from this pin. The voltage reference has a nominal magnitude of 2.5 V and is reference to the VA- pin on the converter. VREFIN - The voltage input to this pin establishes the voltage reference for the on-chip modulator.
31
CS5460
Differential Current Inputs Positive Digital Supply Digital Ground Negative Analog Supply Positive Analog Supply Power Fail Monitor RESET Other
No Connection 8,18 NC - No connection. Pins should be left floating. 15,16 IIN+, IIN- - Differential analog input pins for current channel.
Power Supply Connections
3 4 13 14 17 VD+ - The positive digital supply is nominally +5 V 10% relative to DGND. DGND - The digital ground is at the same level as VA-. VA- - The negative analog supply pin must be at the lowest potential. VA+ - The positive analog supply is nominally +5 V 10% relative to VA-. PFMON - The power fail Monitor pin monitors the analog supply. Typical threshold level is 2.5 V with respect to the VA- pin. Reset - When reset is taken low, all internal registers are set to their default states.
19
7. SPECIFICATION DEFINITIONS
Full Scale Error The deviation of the last code transition from the ideal [{(VREFIN) - (VA-)} - 3/2 LSB]. Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the VIN- or IIN- pin). Units are in LSBs.
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8. PACKAGE DIMENSIONS
24L SSOP PACKAGE DRAWING
N
D
E11 A2 A1 A
E
L
e
b2 SIDE VIEW
END VIEW
SEATING PLANE
123
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025 0 NOM -0.006 0.069 -0.323 0.307 0.209 0.026 0.0354 4 MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041 8 MIN -0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63 0
MILLIMETERS NOM -0.13 1.75 -8.20 7.80 5.30 0.65 0.90 4 MAX 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.75 1.03 8
NOTE
2,3 1 1
JEDEC #: MO-150 Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS279PP5
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